1. Field of the Invention
The invention relates to circuit design that is compatible with multiple voltages. More specifically, the invention relates to an overvoltage-tolerant self-biasing complimentary metal-oxide semiconductor ("CMOS") output buffer for use in mixed-voltage circuit designs.
2. Description of Related Art
In every integrated circuit ("I/C") chip, there is a section called the input/output ("I/O") which contains circuits that condition the signals traveling into and out of the chip. The I/O of the chip contains I/O buffers. The I/O buffers interface, or buffer, the relatively sensitive, low current, circuits in the chip to the relatively high current environment outside of the chip. The I/O buffers are connected between the core circuitry and the pads, where wires or other conductors connect the chip to the external circuitry.
FIG. 1 illustrates a simple CMOS output buffer circuit. The CMOS output buffer circuit includes a first input 105 (N3), a second input 115 (N4), a first voltage input 125, a second voltage input 135, a p-channel metal-oxide semiconductor field-effect transistor (MOSFET) ("pMOS") 100, an n-channel MOSFET ("nMOS") 110, a pad 120 and an output 145. In the enabled mode of operation, inputs 105 and 115 are tied together. When inputs 105 and 115 are high, the pMOS 100 is turned OFF, the nMOS 110 is turned ON, and, therefore, the output 145 is pulled down to the second voltage input 135, or VSS (approximately 0 V). Similarly, when inputs 105 and 115 are low, the pMOS 100 is turned ON, and the nMOS 110 is turned OFF, thereby pulling the output 145 up to the first voltage input 125, or VDD (approximately 2.5 V in this illustration). However, if the voltage at the pad 120 becomes higher than the voltage at the first voltage input 125 (i.e., higher than VDD), then the drain-body junction of the pMOS 100 would become forward-biased resulting in a current flowing from the pad 120 to the first voltage input 125. This current can quickly become large enough to disrupt the operation of the circuit, possibly resulting in permanent damage to the circuit.
To prevent the forward-biasing of the drain-body junction of the pMOS 100, the body must be biased at a potential equal to or greater than the anticipated pad overvoltage, instead of at the first voltage input 125, or VDD. In one conventional method, the bias voltage is obtained from an external voltage source, separate from VDD, that is higher than VDD. This method, however, has many disadvantages. First, an additional external voltage source is required. Next, an additional contact pad and associated metal conductors on and off the chip are required to deliver the bias voltage to the pMOS body. Moreover, the additional pad consumes chip real estate and the conductors add to routing complexity. Finally, the threshold voltage of the output buffer is increased even in the absence of an output pad overvoltage condition because the body of the pMOS device is biased at a fixed voltage that is higher than VDD. This unnecessarily degrades the normal performances of the output buffer.
In another conventional method, the bias voltage is generated on the chip. Although this method does not require an additional external voltage source or a contact pad, nevertheless increases the threshold voltage of the output buffer like the first conventional method described above. In addition, it requires an additional voltage generating circuit on the chip. This results in additional real estate and adds to the power consumed by the chip.
In both of these conventional methods, the maximum allowable pad overvoltage is set by the fixed voltage obtained from an additional external power supply or from an on-chip voltage generator. If the pad overvoltage exceeds the fixed bias voltage of either conventional methods, circuit damage may occur. In other words, the bias voltage is fixed and if the voltage at the pad 120 is higher than the fixed bias voltage, then the problem of forward-biasing arises again, which may damage the pMOS 100, and/or other devices.
In yet another conventional method, the pMOS body potential is derived directly from VDD or from the voltage on the output pad, whichever is greater. This is accomplished by fabricating Schottky-barrier diodes such that the anode of one diode is connected to VDD, the anode of a second diode is connected to the output pad, and the two cathodes are joined and connected to the pMOS body. When the voltage on the output pad is less than VDD, the first diode holds the pMOS body at a potential approximately equal to VDD, and the second diode is reverse-biased, preventing the VDD supply from affecting the output pad. When the voltage on the pad exceeds VDD, the second diode becomes forward-biased, transferring the overvoltage to the pMOS body. The first diode then becomes reverse-biased, preventing the overvoltage from disrupting the VDD supply.
Schottky-barrier diodes are composed of metal-semiconductor junctions. They are widely used in silicon bipolar I/Cs because the turn-on voltage of Schottky-barrier diodes is lower than that of silicon p-n junction diodes (.about.0.3 V compared to .about.0.7 V). Also, less charge is stored in metal-semiconductor junctions than in p-n junctions which allows the metal-semiconductor junctions to turn ON and OFF more quickly. These two characteristics make Schottky-barrier diodes useful for circuit applications requiring fast switching.
The preferred material for fabricating Schottky-barrier diodes is PtSi. Pt, however, is infrequently used in conventional very large-scale integration ("VLSI") CMOS processing. Therefore, the addition of Schottky-barrier diodes into a conventional CMOS technology may require additional processing steps, which increases the processing cost and time, and may decrease the yield.
Thus, from the above discussion, it can be seen that it is desirable to have an overvoltage-tolerant output buffer design that does not require an additional voltage source, contact pad, or processing steps. Furthermore, it is desirable to have an overvoltage-tolerant output buffer design whose degree of overvoltage-tolerance is not limited by a predetermined potential, and whose normal performance is not effected by the circuitry that provides overvoltage-tolerance. Finally, it is desirable to have an overvoltage-tolerant output buffer whose real estate and power requirements are not significantly increased by the circuitry that provides overvoltage-tolerance. Moreover, such an overvoltage-tolerant output buffer design would be especially useful in mixed-voltage systems.